1. Field of the Invention
The present invention relates to a method and apparatus for determining capacitance of a differential cascode voltage swing logic (DCVSL) for use in a timing verifier. More particularly, it relates to a method and apparatus which uses a simplified model of a structure of a DCVSL in determining the capacitance.
2. Discussion of the Related Art
Circuit verification is a significant part of analyzing a design of a circuit. It is significantly more economical to ensure that the circuit will operate as intended prior to production. Timing verification is a portion of the circuit verification process. Timing verification is used to identify all critical and race paths through a circuit. Critical paths are paths through which a signal passes more slowly than other paths. In race paths, the signals pass more quickly. Timing verification has become increasingly important for the design of CMOS circuits. As CMOS circuits on a chip have become more complex, the complexity for verifying timing has also increased. Also, as chips are designed to operate at higher speeds, timing verification must be more accurate. Thus, timing verification is a principal part of the design process for a circuit.
A variety of tools are available for timing verification. These tools involve differing speeds for verification and accuracy of the results. The most significant concern for a circuit designer in timing verification is that a timing induced functional violation will go undetected, i.e. that an error will not be found during the verification process. If a violation is missed by the timing verifier, the circuit will pass to the silicon where errors become more difficult and more costly to uncover and resolve.
One type of timing verification tool is computerized circuit simulators, such as SPICE. With SPICE, the circuit is modeled within the computer. The program simulates the operation of an entire circuit which is represented as a set of connected elements. Certain assumptions are made regarding the inputs. The program then determines the value of signals at all of the points within the circuit at time intervals. While SPICE and other circuit simulators are very accurate models of a circuit, they are extremely slow. They operate with small time segments and make many calculations to determine the signal values at the many nodes in a circuit. This slow speed inhibits their use as a timing verification tool for an entire circuit. Therefore, other timing verification tools have been created which use simpler models of a circuit. These other tools provide much faster speeds, with a loss of accuracy. Since accuracy decreases with such tools, a circuit designer will often use the simpler, quicker tools just to determine potential critical or race paths, or paths which may induce a functional violation. Once certain paths are identified, they will be checked more accurately using SPICE, or a similar circuit simulator, to determine whether any changes need to be made to the circuit.
With a timing verification tool, it is most important not to miss any violations. A missed violation will result in an erroneous circuit, which may not be detected until much later. However, the number of false violations should be minimized. As the number of detected violations increases, the time to accurately check each detected violation also increases. With many false violations being reported by the timing verifier, the time for checking the circuit becomes needlessly large. Therefore, a need exists for a timing verification tool which quickly and accurately estimates minimum and maximum delay times, while erring on the pessimistic side in order to insure that no violations are missed.
Traditionally, the delays through MOSFETs can be calculated by treating them as a resistance-capacitance (RC) structure. By using a model of the corresponding RC structure for a MOS device, the Miller capacitance can be used to determine the maximum and minimum values for delays. The Miller capacitance is used because it is easy to calculate and represent a worst case scenario. However, the difference between capacitances and delays using such models differs significantly from actuality. Such inaccuracies result in large numbers of false violations which need to be checked. Therefore, a need exists for a timing verification tool which more accurately reflects delays and capacitances within the circuit.
Furthermore, when two or more gates of MOS devices are on a single trace, the capacitances of each device are summed to determine the maximum capacitance as seen at the trace. This summing further compounds the errors when certain structures are involved. In particular, the capacitance of differential cascode voltage swing logic (DCVSL) circuits, which include multiple devices on a single trace, are severely miscalculated. A DCVSL circuit, as illustrated in FIG. 1, includes two MOS devices 1, 2 on a single trace 3. When the total capacitance is determined according to conventional practice, both devices are treated as having source/drain pairs which are either rising or falling. However, with the DCVSL structure, one MOS device will have a rising source/drain pair while the other has a falling source/drain pair. It is impossible for both pairs of source/drain nodes to switch in a direction opposite to the input signal. Additionally, the rising source/drain pair passes a reduced charge due to the body effect. Therefore, a need exists for a timing verifier which more accurately identifies the capacitances of a DVCSL structure and can more accurately determine timing.
Of course, greater accuracy could be obtained by simply including the entire circuit in the analysis and using a circuit simulator. However, this type of timing analysis would be extremely slow, which is impractical for a timing verifier seeking to quickly determine potential problems in a circuit design.
The present invention overcomes many of the deficiencies of the existing timing verifiers by more accurately calculating capacitance of each of the MOS devices in a circuit. In accordance with the present invention, the capacitance of the MOS devices is determined based upon a variety of potential inputs to each of the terminals, gate, source and drain. The capacitance at the gates of each of these devices may then be used, in combination, to determine a load capacitance for the DCVSL circuit. By using calculated capacitances and simplified models of DCVSL circuits, the timing verifier can determine a load for the DCVSL circuit fairly quickly.
According to one embodiment, a simplified model for the DCVSL circuit operates to account for the complementary switching behavior of such circuits. According to this model, one of the MOS devices has a source/drain pair which switches in the same direction as the input voltage, and the other MOS device has a source/drain pair which switches in the opposite direction. For symmetrically sized DCVSL circuits, it does not matter which pair is assumed to switch in either direction. For asymetrically sized circuits, the first simplified model switches the device with the larger width opposite in the direction to input signal for determining maximum capacitance and in same direction of the input signal for determining minimum capacitance. The smaller width device has its source/drain pair switching in the opposite direction to that of the larger device.
According to a second embodiment, a second model of DCVSL devices is used. In the second model, the source/drain pair of only one of the MOS devices is switched when the input has switched, which accounts for the possible overlap current due to time delays. The non-switching device is assumed to be connected to VDD or VSS, depending on the behavior of the switching device. For example, with an NMOS DCVSL, the model has one device with its source/drain pair falling and other device tied low, since the logical state it would eventually switch to is high. Again for an NMOS DCVSL device, the model determines the minimum capacitance by having one source/drain pair rising, and the other pair tied high, since it would eventually switch to low. The body effect may also be accounted for on one side of the switching device because one source/drain node could have complementary logic to insure a good voltage output level. Only one node needs to be body effected. With asymmetrically sized DCVSL circuits, the second embodiment uses the larger device as the switching source/drain pair.